DC/DC power management systems generally regulate static or switched-mode DC power levels supplied at a particular voltage/current. Static power management systems condition the output voltage and current to levels that are appropriate for a particular circuit. When operated in a switched-mode, these power management systems are also used to cycle power within a given circuit at time periods that cause the circuit to “turn off” during time intervals when its functions are not absolutely needed by the larger system it serves. Power cycling is particularly important in mobile systems to extend battery life, and when refreshing and clocking data between random access memory and microprocessor systems, particularly in multi-core microprocessor architectures. The concepts presented herein are not limited to DC/DC power systems, and can be similarly applied to AC/DC inverter and AC/AC transformer circuitry with rudimentary understanding of those skilled in the art of power management.
Multi-processor core systems have particular relevance to the present invention. Localized high-speed computing systems co-locate microprocessor, memory, and micro-controller subsystem functions within a processing cell that is wired in parallel with other processor cells. Until recently, higher computing speeds are achieved by distributing instructions across all the cells to allow each cell to work simultaneously on an instruction packet. Fundamental limitations relating to the stability of the clock circuitry that times data transfers within and between each of the subsystems, and the speed and power levels at which external power management circuitry can supply power to the computing cell is now causing the microprocessor to be underutilized. These fundamental limitations now cause the microprocessor of a single cell to operate at 25%-30% of its utilization capacity. Utilization capacities are further reduced when microprocessors are arrayed in parallel. For instance, a 16 core microprocessor array will function slower than a 4 core microprocessor array. The under-utilization of localized microprocessor arrays has motivated the development of cloud computing architectures that distribute computational functions across a computer network, which open undesirable risks to data security in many computational applications. Therefore, it is desirable to provide switched-mode power levels at higher speeds, as well as stable clock circuitry to a single processor or a multi-core processor system.
Thermal management considerations are a principal impediment to achieving these objectives. Power management systems and processor cores generate heat that compromises performance when not adequately managed. The significant heat generated in power management circuitry having less than optimal efficiencies cause it to be physically isolated, typically on another board, from memory, microprocessor, controller circuitry, which generate large amounts of heat in their own right. The physical separation contributes to the less than optimal delivery of power at the speeds necessary to resolve these problems. Methods that produce higher efficiency power management modules which generate lower heat levels permit higher power levels to be supplied by placing the power management device in closer proximity to memory and microprocessor core circuitry. Co-location of high efficiency switched-mode power management devices with one or more processor cells also reduce overall system power losses through much shorter interconnect circuitry. Methods and apparatus that improve supplied power to a processor core are therefore desirable to the enhanced utilization of microprocessor arrays and the improved operational efficiency of high-speed computing systems.
Heat generated by the processor circuitry and any co-located power management device alters the timing of conventional clock circuitry. This causes a need for additional control circuitry to maintain stable clock functionality. Therefore, the development of clock circuitry that remains stable with varying temperature, and the introduction of additional means to reduce the power consumed by semiconductor die in electrical communication with co-located power management systems are also desirable.